Staff RTL Design Engineer

About the role

SiFive is seeking a Staff RTL Design Engineer to join its CPU microarchitecture team. You will work on cutting‑edge RISC‑V CPU cores, driving new features, performance improvements, and ISA extensions from concept to silicon.

Key responsibilities

• Architect, design, and implement new features and ISA extensions in RISC‑V CPU core generators.
• Develop microarchitecture specifications and produce high‑quality documentation.
• Perform initial sandbox verification and collaborate with the verification team on comprehensive test plans.
• Work with the physical implementation team to meet frequency, area, and power targets.
• Partner with performance modelling engineers to explore and optimize performance.

Required profile

• Minimum 5 years of RTL design experience for CPU products.
• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• Strong background in hardware RTL design using Verilog, SystemVerilog, or VHDL.
• Ability to work collaboratively in a fast‑paced, high‑quality engineering environment.

Required skills

• Verilog
• SystemVerilog
• VHDL
• Scala (optional)
• Chisel (optional)
• RISC‑V architecture knowledge (plus)
• Object‑oriented or functional programming language proficiency