Senior Digital Verification Engineer

About the role

Monolithic Power Systems is seeking a Senior Digital Verification Engineer to lead verification of digital and mixed‑signal ICs using industry‑standard ASIC tools. You will work on power management, signal management and mixed‑signal functions for a variety of markets.

Key responsibilities

• Generate verification plans based on design requirements and product datasheets.
• Collaborate with digital and analog designers to develop system‑level and behavioral models.
• Create a verification environment using UVM and SystemVerilog.
• Write digital and mixed‑signal test cases, assertions, and checkers.
• Analyze and debug test results, code coverage and functional coverage.
• Develop verification IPs, standard tests, environments, and automation scripts.

Required profile

• MS in Electrical Engineering with 5‑8 years of ASIC verification experience.
• Strong knowledge of ASIC development processes and digital design techniques.
• Ability to follow design specifications and meet project milestones.

Required skills

• SystemVerilog and UVM.
• Digital simulation, coverage analysis and formal verification tools.
• Scripting languages such as TCL, Python and C++.
• Experience with mixed‑signal verification and gate‑level verification.
• Familiarity with interfaces like I2C, I3C, SPI, USB, PMBUS.