System Validation Engineer (New Grads)
sifive · Hsinchu
Job description
About the role
Join SiFive's System Validation team to work on validation of RISC‑V CPUs using FPGA‑based platforms and bring‑up boards. This position offers extensive exposure to RISC‑V processors, software ecosystem, and development hardware, ideal for early‑career engineers.
Key responsibilities
- Perform root‑cause and failure analysis on RISC‑V CPU hardware and software components.
- Use ILA and JTAG debuggers to troubleshoot and validate FPGA designs.
- Develop and execute systematic failure hypotheses through step‑by‑step elimination.
- Create and maintain Python scripts to automate debug workflows.
Required profile
- Bachelor’s or Master’s degree in Computer Science, Electronics, or Communication Engineering.
- Strong understanding of computer architecture and logic design.
- Positive attitude, proactive learning mindset, and commitment to excellence.
Required skills
- Verilog for logic design and FPGA implementation.
- Experience with Linux operating systems.
- Scripting in Python and BASH.
- Familiarity with ILA and JTAG debugging tools.
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Hsinchu