Senior Design Verification Engineer

About the role

SiFive is looking for a Senior Design Verification Engineer to collaborate with CPU designers, compiler, performance and system verification teams. You will create automated test cases and develop internal processor models to verify hardware designs for RISC‑V based products.

Key responsibilities

• Review product definitions from a verification perspective and work closely with design teams on specifications, test plans and failure analysis.
• Implement internal processor models supporting new RISC‑V features and SiFive‑specific designs.
• Develop tools, test benches and test suites using C/C++, Python and optionally SystemVerilog.

Required profile

• Minimum 3 years of experience with standard verification tools and methodologies (RTL simulation, wave tracing, scripting).
• Strong understanding of processor and SoC architecture or ability to quickly learn it.
• Experience with command‑line embedded software tools (gcc, as, gdb) and high‑level verification flow (test generation, coverage analysis, closure).

Required skills

• C, C++, Python
• SystemVerilog (plus)
• Scala, Chisel
• RTL simulation, wave tracing, scripting languages
• FPGA prototyping and debugging (plus)