Staff RTL Design Engineer

About the role

SiFive is seeking a Staff RTL Design Engineer to join its CPU microarchitecture team. You will help create industry‑leading RISC‑V CPU cores and bring new hardware IP to market quickly and with high quality.

Key responsibilities

• Architect, design and implement new features, performance improvements, and ISA extensions for RISC‑V CPU core generators.
• Develop microarchitecture specifications and produce thorough documentation.
• Perform initial sandbox verification and collaborate with the verification team on test plans.
• Work with the physical implementation team to meet frequency, area, and power targets.
• Partner with the performance modelling team to explore and optimise performance.

Required profile

• 5+ years of RTL design experience for CPU products.
• BS/MS in EE, CE, CS or related field, or equivalent experience.
• Strong attention to detail and a collaborative mindset.

Required skills

• Proficiency in Verilog, SystemVerilog or VHDL.
• Experience with CPU RTL design and microarchitecture.
• Knowledge of RISC‑V architecture (plus).
• Familiarity with Scala and/or Chisel (plus).
• Understanding of at least one object‑oriented or functional programming language.