Software Engineer – Verification IP

About the role

Siemens EDA is seeking a Software Engineer to develop verification IP for high‑speed interfaces and coherency protocols. You will specify, implement, test, and enhance verification components that help customers accelerate chip, board, and system design.

Key responsibilities

• Design and implement verification IP for protocols such as PCIe, USB, Ethernet, DDR5, LPDDR5 and CXL.
• Develop SystemVerilog test benches using UVM/VMM methodologies.
• Create assertions, coverage models, and bus functional models (BFMs).
• Debug, troubleshoot, and resolve customer issues in collaboration with TMEs and Field AEs.
• Maintain documentation and contribute to test plans and coverage analysis.

Required profile

• B.Tech/M.Tech in Electronics, Electrical, Computer Engineering or a related field from a reputable institute.
• 2–6 years of verification engineering experience.
• Strong understanding of verification methodologies (UVM, VMM) and standard bus protocols.
• Effective teamwork, communication, and a willingness to learn new technologies.

Required skills

• SystemVerilog
• UVM
• VMM
• Assertions
• Coverage analysis
• Testbench development
• BFM design
• Debug and logger tools
• PCIe Gen5/Gen6
• USB 3.2
• 400 Gb Ethernet
• DDR5, LPDDR5
• CXL
• SATA, NVMe, Flash

What we offer

• Flexible work model (remote and office options).
• Competitive benefits and rewards.
• Inclusive, diverse workplace culture.
• Opportunity to work on cutting‑edge EDA technologies.