Senior Staff Package Design Engineer - MIS Substrate/FC Expose Die

About the role

Renesas Electronics is looking for a Senior Staff Package Design Engineer in Taipei to design and develop package and interconnect methods for its packaging needs, including Power SiP/modules, wafer-level, flip-chip, multi-chip module and power device packaging. Experience in power or GaN is required.

Key responsibilities

• Design and develop package and interconnect methods for Power SiP/modules, wafer-level, flip-chip, multi-chip module and power device packaging; GaN-related packaging is a plus.
• Qualify package technologies for consumer and industrial power and automotive power applications.
• Benchmark, select and qualify materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).
• Work with OSAT/CM to run DOE, optimize processes, set process specs and resolve issues early so only high-quality parts reach customers.
• Work with product groups and the reliability team to qualify new packages and processes, and help resolve customer complaints.
• Ensure a smooth transition into production and monitor ramp-up.
• Take part in packaging roadmap development and keep technical expertise on advanced packaging methods.
• Establish and maintain package design rules.

Required profile

• Doctorate, Master's or Bachelor's degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.
• More than 10 years of relevant experience in package development, emphasizing power SiP/modules, wafer-level and flip-chip packaging.
• Experience in power or GaN is required.

Required skills

• Strong understanding of power SiP/modules, wafer-level and flip-chip packaging methods, assembly processes and qualification methods.
• SPC and statistical analysis software.
• Wire-bonding and multi-chip module technologies are a plus.
• Strong analytical, presentation, interpersonal and communication skills.