Staff Design Verification Engineer - Cache Verification

About the role

SiFive, a pioneer of RISC-V, is hiring a Staff Design Verification Engineer in Hsinchu to drive verification of cache and memory-subsystem functionality, with an emphasis on cache coherency, ordering, correctness and subsystem integration. This is a staff engineer individual-contributor role in the horizontal cache verification area, working independently on high-quality verification work.

Key responsibilities

• Own verification planning and execution for L2/L3 cache and related cache-subsystem features, from block-level verification through subsystem integration.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus and coverage models for coherency, ordering, flow control and error scenarios.
• Define and run directed and constrained-random tests that expose corner cases in coherency, concurrency, backpressure and integration.
• Analyze failures, isolate root causes and drive fixes across RTL, testbench infrastructure, assertions and test content.
• Collaborate with architecture, design and verification teams to clarify requirements and improve verification quality early.
• Write functional coverage, analyze results and close coverage holes.
• Contribute reusable methodology, automation and debug improvements.

Required profile

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or a related field.
• 7+ years of experience in ASIC, CPU or SoC design verification, with strong hands-on ownership of complex problems at block or subsystem level.
• Strong understanding of computer architecture and microarchitecture fundamentals.

Required skills

• SystemVerilog and UVM-based verification.
• Cache architecture, memory hierarchy and cache coherency protocols/behavior.
• Building reusable testbenches, assertions, checkers, scoreboards, coverage models and debug infrastructure.
• Debugging and root-cause analysis across specification, RTL and testbench.
• Coverage analysis and closure, constrained-random verification, metrics-driven signoff.
• Preferred: multi-level cache verification, multicore verification, performance-oriented verification, formal techniques, emulation/FPGA-assisted debug, Python, C++ or scripting languages.