Senior ASIC Engineer (SoC Integration)

About the role

Micron Technology, a global leader in memory and storage solutions, is hiring a Senior ASIC Engineer in Hsinchu, Taiwan. The role covers SoC integration, PCIe and IP work, and collaboration with architecture, verification, physical design, firmware and validation teams across the full chip development cycle.

Key responsibilities

• Lead top-level SoC integration including CPU subsystem, interconnect, peripheral IPs, clock/power/reset structures and test structures.
• Own SoC RTL integration, lint/CDC/RC checking, synthesis constraints and timing closure support.
• Define and maintain SoC-level interfaces, connectivity and integration specifications.
• Integrate and validate CPU cores or clusters (ARM, ARC, RISC-V or proprietary) and optimize PPA at the CPU and SoC boundaries.
• Collaborate with DFT teams to integrate scan, MBIST, LBIST and boundary scan, and bring up test modes, vectors and patterns before silicon.
• Support pre-silicon simulation and emulation, post-silicon bring-up, and drive root-cause analysis and issue resolution.
• For PCIe: work on high-speed protocols (PCIe, USB, SATA, DisplayPort, HDMI) and contribute to large-scale design projects.
• For IP: write micro-architecture specifications, implement RTL designs and work with verification teams.

Required profile

• MS in Electrical Engineering with 13+ years of experience (SoC/PCIe track).
• MS in Electrical Engineering with 7-10 years of design experience (IP track).
• Knowledge of large-scale design projects is required.
• Preferred: knowledge of NVMe, CXL, DDR and storage/memory protocols; familiarity with high-speed protocols is a plus.

Required skills

• RTL and testbench development in Verilog or SystemVerilog.
• Design/verification tools such as VCS, VC-Spyglass CDC, LINT, RDC, LEC, Design Compiler, Formality and PrimeTime.
• TCL, Perl or Python is a plus.
• Good English communication on technical topics.