Interconnect Design Engineer

About the role

SiFive is seeking a senior hardware engineer to design industry‑leading CPU and interconnect IP for RISC‑V based SoCs. The role focuses on creating highly configurable TileLink interconnect generators using the Chisel hardware construction library embedded in Scala.

Key responsibilities

• Architect, design and implement enhanced TileLink interconnects, cache controllers, protocol bridges, and other uncore logic as RTL generators in Chisel.
• Develop self‑configuring RTL generators that optimise connectivity and support multi‑core and multi‑system coherence.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and improve automatic generation of documentation, verification testbenches and packaged software.
• Collaborate with verification teams to create and execute thorough test plans and maintain high‑quality documentation.

Required profile

• Strong knowledge of cache and cache‑coherency architectures and concepts.
• Experience with Network‑on‑Chip (NoC) or other interconnect fabrics and industry‑standard bus protocols such as AXI, AHB, APB, CHI.
• Solid software engineering background, including functional and object‑oriented programming, templated metaprogramming, and test‑driven development.
• Bachelor’s or Master’s degree in EE, CE, CS or related field, or equivalent experience.

Required skills

• Chisel and Scala for hardware generation.
• RTL design in Verilog, SystemVerilog or VHDL.
• Familiarity with Git, Jira and Confluence.
• Understanding of bus protocols (AXI, AHB, APB, CHI) and cache coherency mechanisms.