Principal Hardware Application Engineer - High-Speed Networking

About the role

Marvell is hiring a Principal Hardware Application Engineer for a hands-on, customer-facing role based in Taipei. You will work closely with customer hardware teams, Marvell's global engineering organization and cross-functional teams including SI/PI and software AE. The position is eligible for Marvell's bonus and equity plans.

Key responsibilities

• Serve as the primary hardware technical focal for strategic accounts and drive design-in from schematic review through board bring-up, EDVT and mass production.
• Review customer PCB schematics and layout files for Marvell DC switch platforms, guiding component selection, power sequencing, clock distribution and high-speed signal routing.
• Perform or coordinate SI and PI simulations (pre- and post-layout) for high-speed Ethernet interfaces at 800G, 1.6T and beyond, evaluating channel performance, SerDes tuning and PAM4 link margin.
• Support hardware bring-up at customer sites and in the Taipei lab, debugging L1 issues such as SerDes link training, power integrity, thermal and interface failures.
• Author and review hardware design guides, application notes, schematic checklists and layout guidelines.
• Join EE/ME/SI/PI design reviews with the global hardware team and represent customer requirements to silicon and platform teams.
• Ramp up knowledge of UALink, ESUN, CPO and 224G SerDes and contribute to internal training.
• Engage suppliers across PCB materials, thermal solutions, power components, connectors and cabling to optimize platform designs.

Required profile

• Bachelor's degree or above in Electrical Engineering, Electronics Engineering or a related field.
• 8+ years of experience in hardware design or hardware application engineering for high-speed networking or data center systems.
• Experience supporting customers through schematic review, layout review, bring-up and EDVT.
• Strong communication skills and a proactive, self-driven style, able to manage multiple customer engagements in parallel.

Required skills

• EE design tools: schematic capture (Cadence OrCAD, Mentor PADS or equivalent) and PCB layout review (Cadence Allegro or equivalent).
• Signal integrity principles: channel loss, eye diagrams, SerDes Tx/Rx equalization and PAM4 link budget.
• Power integrity: PDN design, AC/DC simulation, decoupling strategy and power sequencing.
• Preferred: hands-on experience with DC switch or high-speed Ethernet platforms, SI/PI simulation tools (Sigrity, Ansys SIwave, HFSS, PowerDC), thermal design for high-power switching, MSDC ODM design requirements in Taiwan, and board bring-up tools (oscilloscopes, VNAs, BERT, real-time sampling scopes).