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Principal Engineer, Advanced Package Technology

marvell · Hsinchu City

New
Senior 🇬🇧 English
Cadence Sigrity PowerSI Ansys SIwave Ansys HFSS Cadence Clarity Cadence APD CoWoS EMIB CPO CPC

Job description

About the role

The Marvell Advanced Packaging R&D team develops package design and technology to meet the electrical, mechanical, thermal and system requirements of next-generation HPC, AI and networking solutions. The Principal Engineer leads the packaging technology roadmap for AI XPU, XPU-attach and Switch, working on 2.5D and 3D packages, Co-packaged copper or optics and advanced substrates.

Key responsibilities

  • Develop the packaging technology roadmap and recommend technologies beyond what is currently available, creating and protecting IP
  • Create new package concepts, run routing feasibility, signal and power integrity studies and build proof-of-concept samples
  • Define package architecture including chiplet topology, interposer/substrate scaling, power delivery network strategy and thermal design
  • Lead co-design across silicon design, floorplanning, PDN modeling and mechanical/thermal reliability, and partner with silicon teams on die floorplan, bump map, TSV and RDL
  • Work with OSATs and foundries on process capability, manufacturability, yield and cost, and drive qualification and reliability validation to volume readiness

Required profile

  • Bachelor's or master's degree in mechanical engineering, material science or a related field with 8-10 years of experience, or PhD/post-doc with 5+ years
  • Experience managing substrate and assembly material vendors, substrate manufacturers, OSATs and foundries
  • Experience interfacing with product design teams on floorplanning, package design input and PDN design
  • Ideal candidate: data center AI accelerator, networking silicon or custom HPC silicon background, experience setting roadmaps, silicon disaggregation and memory integration, VNA and TDR measurements, and influencing senior stakeholders

Required skills

  • Signal and power integrity simulations and analysis for 2.5D and 3D packages (Cadence Sigrity PowerSI, Ansys SIwave)
  • EM simulations with Ansys HFSS, SI-Wave, Cadence Clarity
  • Cadence APD or PCB editor for routing feasibility studies
  • Understanding of CoWoS, EMIB, CPO and CPC technologies

What we offer

  • Eligibility for Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers
  • Competitive compensation and benefits

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Source : ats:workday

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Published 7小时前

Expires 1个月后

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marvell

Hsinchu City