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Layout Engineer (Junior/New Grad)

monolithicpower · Taipei - Taiwan

New
Junior 🇬🇧 English
Cadence Virtuoso DRC LVS

Job description

About the role

Monolithic Power Systems is seeking a junior Layout Engineer to support the development of mixed‑signal and analog integrated circuits. You will work closely with the Design, CAD, and Layout Manager to ensure successful chip tape‑out.

Key responsibilities

  • Estimate layout schedules and perform device placement at block level.
  • Implement top‑level block layouts, manage signal matching, shielding, and pad/ESD routing.
  • Conduct DRC and LVS verification and follow the company’s tape‑out procedure.

Required profile

  • Experience with analog or mixed‑signal circuit layout.
  • Ability to create chip plans, estimate die size, and manage project schedules.
  • Capability to resolve DRC/LVS issues and independently complete tape‑out.

Required skills

  • Cadence and/or Virtuoso layout tools.
  • Understanding of analog process fundamentals.
  • Knowledge of pad/ESD rules, shielding techniques, and database verification.

Questions fréquentes

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Source : ats:workday

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Published 8小时前

Expires 1个月后

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monolithicpower

Taipei - Taiwan