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SoC Design Engineer

MediaTek · Hsinchu

New
🇬🇧 English
Synthesis APR DFT Clock planning Place and route Timing closure ECO Physical verification Tcl Perl C++

Job description

About the role

We are looking for a SoC Design Engineer to work on 7nm~3nm design implementation, methodology, and sign‑off.

Key responsibilities

  • Work on 7nm~3nm design implementation, methodology, and sign‑off.
  • Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR sign‑off, and physical verification.
  • Manage schedule, resolve design and flow issues, and drive methodologies and execution.

Required profile

  • MS degree with at least 2 years of experience in EE/CS.
  • Hands‑on SYN/APR/Sign‑off and tape‑out experience in deep submicron technology.
  • Strong communication skills.

Required skills

  • Synthesis
  • APR
  • Sign‑off
  • DFT
  • Floorplanning
  • Clock planning
  • Place and route
  • Timing closure
  • ECO
  • IR sign‑off
  • Physical verification
  • Tcl
  • Perl
  • C
  • C++

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Published 1小时前

Expires 1个月后

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