SoC Chip Design Engineer for DFT/DFM

About the role

The successful candidate will lead DFT and DFM methodologies, design, and implementation for advanced automotive system‑on‑chip (SoC) designs, working closely with design and layout teams.

Key responsibilities

• Design SoC testing architecture.
• Support NPI to mass production, including test program development, coverage enhancement, yield improvement and cost reduction.
• Collaborate with IP, test engineers, process and board design teams to meet CP/FT/SLT test requirements.

Required profile

• Minimum 3 + years experience in DFT/DFM for automotive ADAS SoC chip design.
• Familiarity with automotive quality and reliability standards such as ISO 26262 and AEC‑Q100.
• Experience in automotive semiconductor manufacturing processes, reliability and yield improvement.

Required skills

• Strong knowledge of SCAN, MBIST, BIST and DFT design structures.
• Expertise in DFM techniques for yield, test time and cost reduction.
• Proficiency with SoC design tools (synthesis, static timing analysis, formal verification).
• RTL coding and scripting (TCL, Perl, Python).
• Knowledge of automated testing equipment (ATE) and test program development.
• Experience with EDA tools such as Mentor Graphics Tessent, Synopsys DFTMAX, and automotive LBIST.
• ATPG pattern generation and coverage analysis for automotive SoC.
• High‑performance and low‑power design methodologies.