Senior Signal Integrity Engineer

About the role

DriveNets is seeking an experienced Senior Signal Integrity Engineer to join its Hardware Engineering team. You will be responsible for ensuring optimal signal integrity of high‑speed interfaces such as 112 Gbps Ethernet, PCIe Gen5, and DDR5, and for integrating SI considerations throughout the hardware design flow.

Key responsibilities

• Perform signal‑integrity simulations and analyses for high‑speed serial links, including loss, jitter, and eye‑diagram assessments.
• Develop and enforce SI guidelines for PCB layout to achieve low‑loss, high‑performance signal paths.
• Identify and resolve SI issues such as reflections, crosstalk, and PDN noise.
• Collaborate with layout engineers to optimize designs and ensure compliance with electrical standards.
• Run pre‑ and post‑layout simulations using tools like Ansys SIWAVE, HFSS, and validate results with measurements.

Required profile

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering.
• 10+ years of hands‑on experience in signal‑integrity analysis for high‑speed interfaces.
• Strong knowledge of EM concepts, transmission‑line theory, and PCB layout for high‑speed designs.
• Excellent communication skills and ability to work in cross‑functional teams.

Required skills

• Ansys SIWAVE, HFSS (or equivalent EM simulation tools).
• HSPICE for model development and circuit simulation.
• Time‑domain and frequency‑domain analysis, jitter and eye‑diagram evaluation.
• PCB layout techniques for Ethernet, PCIe, DDR5 and other high‑speed standards.
• Transmission‑line theory and electromagnetic (EM) analysis.

What we offer

• Opportunity to work on cutting‑edge 112 Gbps PAM4 Ethernet, PCIe Gen5, and DDR5 technologies.
• Access to advanced simulation tools and techniques.
• Deep involvement in high‑speed PCB design and power‑integrity simulations.
• Collaborative environment within a leading high‑speed electronics company.