Senior Power Integrity Engineer

About the role

DriveNets is seeking a highly motivated Power Integrity Engineer to join its Hardware Engineering team. In this role you will define, analyze, simulate and validate power delivery networks for next‑generation networking platforms that support high‑performance ASICs, advanced SerDes interfaces, optical modules and AI‑scale networking systems.

Key responsibilities

• Lead Power Integrity activities throughout the hardware development lifecycle, from architecture through production.
• Define and optimise board‑level and package‑level Power Delivery Networks for high‑current networking ASICs and supporting devices.
• Perform pre‑layout and post‑layout PI simulations using industry‑standard tools and establish target impedance requirements.
• Analyse DC voltage drop, AC impedance, transient response and overall power distribution performance.
• Collaborate with PCB layout engineers to optimise stack‑ups, plane structures, decoupling strategies and power routing.
• Work with Signal Integrity engineers to co‑optimise high‑speed interfaces.
• Develop Power Integrity design guidelines and best practices for next‑generation networking products.
• Support schematic reviews, layout reviews and design sign‑off activities.
• Conduct laboratory measurements and correlate results using oscilloscopes, VNAs, power analyzers and current probes.
• Investigate and resolve PI‑related issues during board bring‑up, validation and production.

Required profile

• B.Sc. or M.Sc. in Electrical Engineering.
• 5+ years of experience in Power Integrity, hardware design or related disciplines.
• Strong understanding of power delivery networks, decoupling methodologies and target impedance concepts.
• Hands‑on experience with PI simulation tools such as Cadence Sigrity, Ansys SIwave, Ansys HFSS or PowerDC.
• Experience designing high‑layer‑count PCBs for networking, telecom, server or data‑center products.
• Knowledge of high‑speed digital systems and interaction between Signal Integrity and Power Integrity.
• Experience with multi‑phase voltage regulators, power sequencing and power management architectures.
• Familiarity with PCB materials, stack‑ups and manufacturing constraints, and with lab validation techniques.

Required skills

• Cadence Sigrity PowerSI / OptimizePI
• Ansys SIwave and Ansys HFSS
• PowerDC or equivalent simulation tools
• High‑layer‑count PCB design for networking and data‑center applications
• Multi‑phase voltage regulator design and power sequencing
• Knowledge of high‑speed SerDes (112G/224G/448G PAM4) and Ethernet (400G‑1.6T) technologies
• Package‑level Power Integrity and advanced packaging techniques
• Optical networking platforms and co‑packaged optics
• Thermal and mechanical effects on PDN performance
• EMI/EMC considerations in high‑density networking systems