Senior Design Engineer - Die-to-Die Interface

About the role

We are looking for a Senior Design Engineer to lead the development of Die‑to‑Die (D2D) and UCIe digital IP for high‑performance computing (HPC) system‑on‑chips. The role involves close collaboration with mixed‑mode designers and firmware engineers to deliver robust, high‑speed interfaces.

Key responsibilities

• Develop D2D and UCIe digital IP blocks targeting HPC SOCs.
• Integrate D2D controller and PHY, achieving timing closure and implementing Design‑for‑Test (DFT) strategies.
• Define interface specifications and create comprehensive verification plans.
• Support integration activities and physical implementation of the IP.
• Collaborate with mixed‑mode design teams and firmware engineers throughout the development cycle.

Required profile

• Master’s degree in Electrical Engineering or Computer Engineering.
• At least 5 years of experience in digital design and verification.
• Strong understanding of digital design and integration flows.
• Familiarity with the UCIe standard (preferred).
• Knowledge of AMBA protocols, especially AXI and CHI (preferred).

Required skills

• Digital design and verification.
• UCIe interface development.
• AMBA protocol expertise (AXI, CHI).
• Timing closure techniques.
• Design‑for‑Test (DFT) implementation.