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PCB Layout Engineer

Kandou AI · Taipei

New
🇬🇧 English
controlled impedance routing differential pair routing length matching via management EMC/EMI design Cadence Allegro Mentor Xpedition PADS Gerber ODB++

Job description

About the role

Kandou is looking for an experienced PCB Layout Engineer to own the complete layout flow for its AI‑focused board products. You will translate hardware schematics into high‑quality, manufacturable designs while ensuring signal and power integrity, thermal performance, and compliance with DFM guidelines.

Key responsibilities

  • Own and execute PCB layout design from initial floorplan through final fabrication and assembly data release.
  • Translate hardware schematics into DFM‑compliant layouts, incorporating SI/PI, thermal and mechanical constraints.
  • Define and document layer stack‑up, impedance requirements, and fabrication specifications in coordination with PCB fab partners.
  • Generate, verify and release complete fabrication and assembly output packages (Gerber/ODB++, drill files, assembly drawings, BOM) ensuring accuracy.

Required profile

  • 5+ years of professional PCB layout experience, preferably in semiconductor, server hardware or high‑speed electronics.
  • Bachelor’s degree in Electrical Engineering, Electronics Engineering or a related technical field.
  • Fluent English communication; Mandarin proficiency is a plus for local coordination.
  • Proven ability to manage workload and meet layout milestones in line with project schedules.

Required skills

  • High‑speed PCB layout: controlled impedance routing, differential pair routing, length matching, via management.
  • Power delivery network design, decoupling capacitor placement, multi‑power‑domain plane design.
  • EMC/EMI design guidelines implementation and layer stack‑up definition.
  • Proficiency with Cadence Allegro, Mentor/Siemens Xpedition or PADS PCB design tools.
  • Experience applying IPC standards (IPC‑2221, IPC‑2222, IPC‑6012) and DFM/DFA guidelines.
  • Generation and review of Gerber/ODB++ output, assembly drawings and BOMs.
  • Integration of signal‑integrity and power‑integrity guidelines into physical layout.
  • Familiarity with PCB fab and OSAT ecosystems in Taiwan/Asia.

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Published 3小时前

Expires 1个月后

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Kandou AI

Taipei