Lead FPGA / CPLD Engineer (Server & Storage)

About the role

Jabil is looking for a Lead FPGA / CPLD Engineer in Sanchong to lead a CPLD/FPGA engineering team that designs and builds Server & Storage products. The role covers both strategic and tactical contributions to CPLD/FPGA design and provides leadership to the design team and other cross-functional disciplines. Domestic and international travel is required.

Key responsibilities

• Lead a CPLD/FPGA engineering team for Server & Storage product development.
• Define CPLD/FPGA design strategy, architecture and roadmap aligned with product requirements.
• Work closely with Hardware, BIOS, BMC and Firmware teams on design, validation and maintenance.
• Drive the implementation of new technologies and design concepts in CPLD/FPGA.
• Establish and enforce RTL coding standards, design review processes and best practices.
• Own test plan development, design specifications and issue tracking for CPLD/FPGA deliverables.
• Mentor and develop junior and senior engineers.

Required profile

• Bachelor's or Master's degree in Electrical Engineering, or equivalent work experience.
• Minimum 8 years of experience in CPLD/FPGA development in the server/storage industry.
• Experience with 1st-tier brand customers on server/storage systems (ODM/OEM) and team leadership is highly preferred.
• Strong organizational, prioritization and analytical skills, with decision-making aligned to the organization's goals.

Required skills

• Expert-level CPLD/FPGA design and Verilog/VHDL coding.
• I2C, SPI, UART and SGPIO protocols.
• RTL coding, simulation and verification, with Git version control and test bench development.
• Understanding of server/storage product architecture and development lifecycle.