DFT Engineer – Advanced Process Platform (Scan, MBIST, BSD)

About the role

Join MediaTek's DFT for Advanced Process Platform team, where you will directly influence Cloud ASIC reliability and yield on cutting‑edge nodes such as N4, N3 and N2. The role focuses on defining and inserting DFT architectures that enable high‑quality test and diagnosis for complex SoCs and chiplet/3D‑IC designs.

Key responsibilities

• Define and implement Scan (full‑scan, compressor), MBIST and Boundary‑Scan/JTAG strategies, owning end‑to‑end insertion flows with Synopsys and Siemens (Tessent) EDA tools.
• Develop and optimise ATPG patterns for stuck‑at, transition‑delay, cell‑aware and path‑delay fault models, driving fault‑coverage closure and DRC‑clean pattern delivery.
• Validate DFT logic through gate‑level simulation (VCS/Xcelium), resolve rule violations and coverage gaps before tape‑out.
• Lead post‑silicon bring‑up activities including CP, FT, HTOL and HVS test‑mode validation, scan‑chain continuity, MBIST execution and repair verification.
• Perform volume diagnosis and yield‑ramp analysis using scan and memory‑BIST data to support yield improvement and RMA processes.

Required profile

• Proactive and self‑driven, taking full ownership and driving issues to closure across multiple teams.
• Passionate about leading‑edge process technology and Cloud ASIC trends, with genuine curiosity about how advanced nodes affect testability.
• Thrives in fast‑paced, ambiguous environments and continuously learns emerging EDA capabilities and best practices.
• Effective communicator able to collaborate in English and Mandarin with design, process, ATE and yield engineering teams.

Required skills

• Strong knowledge of DFT architectures: Scan chains (full/compressor), MBIST (March algorithms, memory repair), Boundary‑Scan (IEEE 1149.x/1687 IJTAG).
• Hands‑on experience with Synopsys DFT Compiler, TetraMAX ATPG and/or Siemens (Tessent) Scan/Memory‑BIST/Diagnosis tools.
• Scripting for flow automation (Tcl, Python, Perl) and RTL integration (Verilog/SystemVerilog).
• Gate‑level simulation expertise using VCS or Xcelium, and familiarity with advanced fault models (cell‑aware, transition‑delay, path‑delay).