Design Engineer - Die-to-Die Interface

About the role

Join our next‑generation HPC SoC team to build cutting‑edge chiplet interconnect solutions. Whether you are an experienced architect or a recent graduate with strong fundamentals, this role offers a clear path to becoming a specialist in UCIe, D2D, and advanced packaging technologies.

Key responsibilities

• Develop die‑to‑die and UCIe digital IP for HPC SoC, delivering high‑bandwidth, low‑latency communication across chiplets.
• Integrate D2D controller and PHY to achieve timing closure and implement design‑for‑test (DFT) strategies.
• Define interface specifications, create verification plans, and support physical implementation.
• Collaborate with mixed‑mode designers and firmware engineers to debug integration issues and ensure seamless hardware‑software co‑design.

Required profile

• Master’s degree in Electrical Engineering or Computer Engineering.
• Experience in digital design and verification.
• Familiarity with digital design and integration flow.
• Knowledge of the UCIe standard (preferred).
• Knowledge of AMBA protocols, especially AXI and CHI (preferred).

Required skills

• Digital design
• Verification
• UCIe standard
• AMBA AXI protocol
• AMBA CHI protocol
• Timing closure
• Design‑for‑Test (DFT)