Chip Architect, Optical, SerDes PHY

About the role

We are looking for an experienced Chip Architect to define next‑generation optical I/O architectures for high‑bandwidth AI, HPC, and networking systems. The role focuses on system and chip architecture development, technology evaluation, and cross‑functional technical leadership.

Key responsibilities

• Define architecture for optical I/O subsystems and optical engines integrated with ASICs, AI accelerators, or networking SoCs.
• Drive trade‑off studies covering bandwidth, latency, power efficiency, scalability, reliability, and cost.
• Develop system‑level models and simulations to evaluate optical interconnect performance.
• Define interfaces, protocols, and architectural requirements for next‑generation high‑bandwidth interconnects.
• Collaborate with ASIC, PHY, photonics, packaging, and system teams to align architecture with product requirements and technology roadmaps.
• Perform end‑to‑end optical link architecture definition, link‑budget analysis, and feasibility studies.
• Guide high‑speed electrical and optical PHY design, including SerDes, PAM4 signaling, equalization, and clock recovery.
• Evaluate emerging technologies for optical I/O, chiplet interconnects, and heterogeneous integration, and develop proof‑of‑concept prototypes.

Required profile

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, Photonics, or related discipline.
• Proven ability to lead cross‑functional technical discussions and architecture reviews.
• Strong written and verbal communication skills with the ability to influence technical direction across multiple engineering disciplines.

Required skills

• Chip, system, and interconnect architecture development.
• High‑speed communication systems and optical interconnect technologies.
• System‑level modeling and performance analysis (MATLAB/Simulink, SystemVerilog).
• High‑speed SerDes architectures and modern PHY technologies.
• Signal integrity and communication system analysis tools.
• Quantitative modeling of architectural trade‑offs.